1. Field of the Invention
Embodiments of the present invention generally relate to a technology for forming metal lines in a semiconductor device.
2. Description of Related Art
In accordance with the ongoing reduction in size of semiconductor devices, the cross sectional area of a semiconductor line is continually reduced, causing a rise in current density. As a result, electromigration (EM) in the metal lines severely reduces reliability. Accordingly, active research and development has been done on the use of different materials for the metal lines in semiconductor devices. For example, Cu has excellent reliability while having lower resistivity than aluminum (Al). However, Cu is difficult to form into a compound with a high enough volatility to easily form micro patterns using a dry etch process.
In order to address the difficulty of patterning Cu lines, a damascene process has been introduced. The damascene process, which employs chemical mechanical polishing (hereinafter referred to as ‘CMP’), includes depositing an inter metal dielectric (hereinafter referred to as ‘IMD’), forming trenches, that is, interconnection areas by patterning the IMD using a photolithography process, gap-filling the trenches with Cu, and polishing the gap-filled Cu layer using CMP, thus forming the Cu lines.
A dual damascene process, which is now generally used in a multi-layered metal line, can accomplish formation of vias and metal lines at the same time with one CMP process.
This dual damascene process is described in detail below with reference to the drawings.
FIGS. 1A to 1C are flowcharts illustrating conventional steps of forming the Cu line of a semiconductor device.
Referring to FIG. 1A, a first interlayer insulating film (e.g., nitride film) 102, a first IMD 104, and a second interlayer insulating film 106 are sequentially deposited over an upper IMD 100 of a semiconductor substrate. The first interlayer insulating film 104 and the second interlayer insulating film 106 are patterned using a photolithography process, thus forming via holes and trenches, that is, line areas. The via holes may be formed first and the trenches may be formed second, or vice versa.
An anti-diffusion film 108 made of Ta/TaN is formed on the via holes and the trenches. A seed Cu layer 110 is formed on the anti-diffusion film 108. The trenches are then gap-filled with a main layer of Cu using an electroplating method, as shown in FIG. 1B. The main Cu layer is polished using CMP, thereby forming Cu lines as shown in FIG. 1C.
When the Cu metal lines are formed using a general dual damascene as described above, the anti-diffusion film 108 made of Ta/TaN and formed in the vias and trenches functions to prevent the subsequently deposited Cu from diffusing into an insulating film.
In the conventional method of forming the Cu metal lines as described above, an irregular surface can result between the anti-diffusion film 108 and the seed Cu layer 110 due to failure in adhesive force, oxidization, corrosion, or for some other reason. Consequently, delamination or lifting occurs between layers due to a stress difference caused by a subsequent anneal process or physical force when Cu CMP is performed.